A major problem experienced by semiconductor chips when handled by humans, such as during packaging or testing, is damage by electrostatic discharge. Charge builds up on people and on tools used by people. When people or charged objects contact a chip, the charge is released with a large voltage surge. This voltage surge can easily damage unprotected chip inputs. Similarly, a very large scale integrated circuit (VLSI) chip in an electronic system is susceptible to voltage and current surges that occur in the system.
In conventional circuits built in bulk silicon, protection circuits typically consist of large area diodes to ground and power. In silicon-on-insulator (SOI) technology, however, devices are built in a very thin silicon film that, in turn, is positioned on an insulating layer. As a result, junctions are lateral, rather than vertical. Thus, a large area diode would require an enormous amount of chip area.
It has previously been proposed for SOI that MOS transistors built in the silicon film be used as protect devices. However, MOS transistors are not as reliable nor as good a protection scheme as are diodes. Furthermore, current conduction is still limited in a very thin silicon film. In electrostatic discharge (ESD) events, large currents flow. Thus, in order to meet the thermal requirements expected for an ESD current in such films, the protect circuits must still be quite large.
It has also been proposed that a vertical protect diode could be formed for SOI technology by etching a contact through the buried oxide and forming a diode with the substrate. However, although this technique is quite useful for making a rectifying contact with the substrate, it primarily protects against negative transients. Positive transients must also be protected against.